What it is
Hardware design from CSE 320 Digital Systems Design, labs 5 and 6, targeting Xilinx Vivado for FPGA synthesis.
What I built
- A synthesizable MIPS-style processor, with demo programs written in MIPS assembly.
- A parameterized matrix-multiply unit, plus a memory-backed variant.
- A self-checking testbench, so the simulation reports pass or fail on its own instead of needing someone to read waveforms.